In a bolometer-type infrared imaging apparatus, infrared signals are extremely low in level. Hence, in a readout circuit, variances other than infrared signals need to be suppressed. Among the important items of characteristics of the readout circuit, there are a circuit noise, a high temperature spurious signal and temperature drift of the circuit. It is noted that smaller the values of these characteristics are desirable to improve characteristics of the readout circuit.
In the conventional bolometer-type infrared imaging apparatus, an operational amplifier (opamp) is used in a portion of the circuit of the apparatus to reduce temperature drift or to eliminate the high temperature spurious signal. Reference is had to Patent Documents 1 and 2 showing a bolometer-type infrared imaging apparatus employing an operational amplifier for the purpose of reducing temperature drift and eliminating high temperature spurious signals.
FIG. 4 shows an overall configuration of the apparatus disclosed in Patent Document 1, that is, the circuit configuration of an imaging apparatus including a readout circuit and its periphery. The circuit comprises a two-dimensional matrix array of thermo-electric devices 202 and is adapted to sense and output received infrared signals from device to device. The infrared signals may be processed in parallel by readout circuits 206 connected to the thermo-electric devices 202 via pixel switches 201 and horizontal switches 204 as selected by a vertical shift register 205. Outputs of the readout circuits are sequentially output to output terminal 210 by horizontal shift register 208. The thermo-electric devices 202 are two-dimensionally arranged on a substrate and sequentially selected based on the switching operations of the pixel switches 201 and horizontal switches 204. The pixel switches 201 are arranged at points of intersection of signal lines 203 and scan lines 211. Each pixel switch 201 is an NchMOSFET having a source grounded, having a drain connected via thermo-electric device 202 to the signal line 203 and having a gate connected to a scan line. The signal line 203 is connected via horizontal switch 204 to the readout circuit 206, an output of which is connected via a multiplexer switch 207 to an output buffer 209. The multiplexer switches 207 are on/off controlled by the horizontal shift register 208. To read signals of the thermo-electric devices 202, the readout circuits 206 are provided at every two columns of the matrix. The vertical shift register 205 sequentially selects the rows of the matrix, while the horizontal shift register 208 sequentially selects the multiplexer switches 207 to deliver outputs of the readout circuits 206 to the output buffer 209.
FIG. 5 depicts an illustrative configuration of a readout circuit disclosed in Patent Document 1. Input voltages VBOL and VCAN are supplied via input voltage lines to a readout circuit 134. This readout circuit includes a bias circuit 141, a bias cancellation circuit 142 and an integrator (integrating operational amplifier) 116. The bias circuit applies a constant voltage to a thermo-electric device 102, and the bias cancellation circuit removes the offset current other than the signals of an object being imaged. The integrator (integrating operational amplifier) is connected to a connection node of the bias circuit 141 and the bias cancellation circuit 142.
The readout circuits 134 operates in parallel simultaneously. Resistance changes of the respective thermo-electric devices 102, corresponding to the strength of infrared incident light from the object being imaged, are detected as current difference between the current through the thermo-electric device 102 as determined by the voltage VBOL and that through the bias cancellation circuit 142 as determined by the voltage VCAN. The so detected current difference is integrated by an integrator 116 and simultaneously transformed into a corresponding voltage value, which is output.
In more detail, referring to FIG. 5, the bias circuit 141 includes an NchMOSFET 104, referred to below as a bias transistor 104, and an operational amplifier 105, referred to below as operational amplifier 105. The bias transistor 104 has its source connected to one end of the thermo-electric device 102. The operational amplifier 105 has an output terminal connected to the gate of the bias transistor 104, while having an inverting input terminal (−) connected to the source of the bias transistor 104. A bias voltage 108 is applied to the non-inverting input terminal (+) of the operational amplifier 105. The bias transistor 104 has a source connected via a horizontal switch 103 to the thermo-electric device 102. It is noted that a switch 101 connected between the thermo-electric device 102 and the ground GND operates as a pixel switch.
The bias circuit 141 applies a constant voltage to each thermo-electric device 102 to transform a change in resistance of the thermo-electric device 102 into a corresponding current value. By this configuration, the bias circuit 141 is able to control the voltage, applied to the thermo-electric device 102, with high accuracy, thereby removing the effect of the temperature coefficient of the gate-to-source voltage VGS of the bias transistor 104 (temperature drift). Further, the bias circuit 104 drives the bias transistor 104 with low impedance to suppress stray noise in each readout circuit 134.
The drain current of the bias transistor 104, that is, the current of the thermo-electric device 102, includes, in addition to the infrared signal component, a significant offset component, on which is present an extremely low level of a signal component from an object being imaged. The bias cancellation circuit 142 is provided to remove this offset component.
The bias cancellation circuit 142 includes a bias cancellation resistor 109, a PchMOSFET 111 and an operational amplifier 112. The bias cancellation resistor 109 has one end connected to a power supply. The PchMOSFET 111, which is also referred as a canceller transistor, has a source connected to the other end of the bias cancellation resistor 109. The canceller transistor 111 has a gate connected to an output terminal of the operational amplifier 112, while having a source connected to an inverting input terminal (−) of the operational amplifier 112, the non-inverting input terminal (+) of which is supplied with a bias cancellation voltage 114. The canceller transistor 111 has a source connected to a power supply VCC via series resistances of the bias cancellation resistor 109 and a switch 110. Thus, as with the bias circuit 141, the bias cancellation circuit 142 is configured to exercises control to remove the effect of the gate-to-source voltage VGS of the canceller transistor 111. With the bias cancellation resistor 109, the stray noise of each readout circuit may be suppressed because the canceller transistor 111 is driven with a low impedance.
The connection node of the drain of the bias transistor 104 and the drain of the canceller transistor 111 is connected to a connection node of the inverting input terminal (−) of an operational amplifier 116 (integrator) and one ends of capacitors 119 and 122 for integrating current variations of the thermo-electric device 102. The capacitors 119 and 122 are referred to as integrating capacitors. The opposite ends of the integrating capacitors 119 and 122 are connected common to the output terminal of the operational amplifier 116, the non-inverting terminal (+) of which is connected to VCC/2 (one-half of the power supply voltage). The inverting input terminal (−) of an operational amplifier 116, that is, the drains of the bias transistor 104 and the canceller transistor 111, are normally fixed at VCC/2. The integrated voltages of the integrating capacitors 119 and 122 are taken out at an output terminal of the operational amplifier 116 and sequentially output at an output terminal 140 from plural readout circuits 134. Meanwhile, control of switches 118 and 121, connected to one ends of the integrating capacitors 119 and 122, and switches 120 and 123, connected between the opposite ends of the integrating capacitors 119 and 122 and the output terminal of the operational amplifier 116, is not described herein and reference is had for details to the disclosure of Patent Document 1. The integrating capacitors 119 and 122 are also referred to as integrating/holding capacitors.
A reset switch 125 is connected between the inverting input terminal (−) and the output terminal of the operational amplifier (integrator) 116. The voltage at the inverting input terminal (−) of the operational amplifier 116 is set to VCC/2, a voltage at the non-inverting terminal (+) of the operational amplifier 116, by turning the switch 125 ON after outputting the voltage integrated by the integrating capacitors 119 and 122.
FIG. 6 shows the configuration disclosed in Patent Document 2. Referring to FIG. 6, a resistance array 301 (R-Array) includes a set of resistors, for example, a set of bolometers having resistance values changed by incident infrared rays. These resistors are arrayed in column and row directions in a two-dimensional matrix and a plurality of readout circuits 302 are arranged on its column side. Each readout circuit 302 includes a bias transistor 304 (NMOS transistor), an operational amplifier 305, a canceller transistor 307 (PMOS transistor) and an operational amplifier 308. An operational amplifier 309 (integrating amplifier) has an inverting input terminal (−) connected to a connection node of the drains of the bias transistor 304 and the canceller transistor 307. The non-inverting terminal (+) of the operational amplifier 309 is supplied with a constant voltage 310. An integrating capacitor 303 and a switch 311 are connected in parallel between the output terminal and the inverting input terminal (−) of the operational amplifier 309. To compensate for resistance variations of the resistances of the R-array 301, multi-valued voltage generators 317, 318, multi-valued voltage buses 315 and 316, and multi-valued voltage selection switches 313 and 314 within each readout circuit 302, are provided between the bias power supply terminal, bias canceller power supply terminal and the non-inverting input terminals (+) of the operational amplifiers 305 and 308. The multi-valued voltage generators adjust the voltages to be supplied to the resistors from one readout circuit 302 to another. The multi-valued voltage buses transmit voltages to the readout circuits. This circuit configuration allows selecting one voltage from the multi-valued voltage buses. The readout circuits 302 may be run in parallel to carry out integration to provide longer integrating time, thereby reducing the noise.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2003-318712A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2004-20325A